This application is related to copending applications entitled xe2x80x9cOPTIMIZATION OF ABUTTED PIN HIERARCHICAL PHYSICAL DESIGNxe2x80x9d by Dahl et al., filed on Nov. 15, 2000, Ser. No. 09/714,722 and xe2x80x9cMETHOD AND SYSTEM FOR AUTOMATICALLY GENERATING LOW LEVEL PROGRAM COMMANDS AS DEPENDENCY GRAPHS FROM HIGH LEVEL PHYSICAL DESIGN STAGESxe2x80x9d by Levine et al., filed on Nov. 13, 2000, Ser. No. 09/712,418, which are both incorporated herein by reference.
The present invention relates to the field electronic design automation (EDA). More specifically, embodiments of the present invention relate to an EDA system having an improved physical design system for hierarchical integrated circuit designs.
An electronic design automation (EDA) system is a computer system used for designing integrated circuit (IC) devices. The rapid growth of the complexity of modern electronic circuits has forced electronic circuit designers to rely upon computer programs to assist or automate most steps of this design process. Typical circuits today contain hundreds of thousands or millions of individual pieces or xe2x80x9ccells.xe2x80x9d Such a design is too large for a circuit designer or even an engineering team of designers to manage effectively without computer systems.
In general, the EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates this high level design language description into netlists of various levels of abstraction. At a higher level of abstraction, a generic netlist is typically produced based on technology independent primitives. The generic netlist can be translated into a lower level technology-specific netlist based on a technology-specific library that has gate-specific models for timing and power estimation, for instance. A netlist is a description of the electronic circuit which specifies what cells compose the circuit and which pins of which cells are to be connected together using wires (xe2x80x9cnetsxe2x80x9d). Importantly, the netlist does not specify where on a circuit board or silicon chip the cells are placed or where the wires run which connect them together. A netlist describes the IC design and is composed of nodes (elements) and edges, e.g., connections between nodes, and can be represented using a directed cyclic graph structure having nodes which are connected to each other with signal lines. A single node can have multiple fan-ins and multiple fan-outs. The netlist is typically stored in computer readable media within the EDA system and processed and verified using many well known techniques.
FIG. 1 illustrates a typical integrated circuit design netlist that includes a number of hierarchical organized cells including a top level block 40 having a number of lower level circuit blocks 10-30 within. Each circuit block 10-30 includes a number of cells and or other blocks.
Once the netlist is complete, the actual physical size, dimensions, geometry and placement of the cells within the blocks can be determined. Determining this geometric information is the function of an automatic placement process and an automatic routing process, both of which are parts of the xe2x80x9cphysical designxe2x80x9d process and are typically computer programs. The designer supplies the netlist into the computer implemented automatic cell placement process. The automatic placement computer program finds a location for each cell on a circuit board or silicon chip. The locations are specified, typically, in two dimensional spatial coordinates, e.g., (x, y) coordinates, on the circuit board or silicon chip. The locations are typically selected to optimize certain objectives such as wire length, wire routibility, circuit speed, circuit power consumption, and/or other criteria, and typically subject to the condition that the cells are spread evenly over the circuit board or silicon chip and that the cells do not overlap with each other. The output of the automatic cell placement process includes a data structure including the (x, y) position for each cell of the design.
Typically, placement is done in two steps including a first coarse placement process, then detailed a placement process. The coarse placement process finds approximate cell locations which optimize the desired metrics and spreads cells evenly across the silicon chip or circuit board. In the output data structure, some cells still overlap and no cells are in legal site locations, so the coarse placement needs to be legalized before the circuit can be fabricated. The detailed placement inputs the data structure output by the coarse placement and generates the detailed placement which does not have overlap and all are located on legal sites.
Next, the designer supplies the netlist and the cell location data structure, generated by the placement program, to a computer implemented automatic wire routing process. This computer program generates wire geometry within data structure. The wire geometry data structure and cell placement data structure together are used to make the final geometric database needed for fabrication of the circuit.
In executing the above physical design programs or xe2x80x9cdesign tools,xe2x80x9d many low level commands with associated parameters, options, variables and target databases are required. In some instances, up to 1,000 of these commands may be required to merely place one block. The commands perform low level functions for the design tools, e.g., a placer, such as: 1) initializing the placer for placement; 2) performing placement on a block; 3) evaluating the result; 4) formatting the data so that it can be understood; and 5) preparing the data for the next stage in the physical design process. Therefore, while the concept of performing a placement on a block can be abstracted to a high level operation, the actual commands given to the design tool to implement that operation are quite volumous.
Furthermore, physical design tools need to be executed on each block separately and then on the whole design. Separate sets of commands are required for each block that is to be processed. During the placement, other design tools may be required to check for any design rule violations or to perform optimizations, or to add special resources such as clocks and power lines, etc. The above process is then repeated for routing. As a result, multiple sets of commands are required for each physical design process to be completed and these commands are repeated over each block. In short, the actual command set required of the designer to merely place and route the netlist 40 of FIG. 1 may require tens of thousands of low level commands which need to be input to the physical design tools in a particular order.
In an effort to address the daunting task of managing these commands, chip designers have written small xe2x80x9cexecutexe2x80x9d programs that function to access a block of the netlist and depending on which block is obtained, apply a predetermined set of commands to the block involving the physical design tools. Once a block is processed, the next one is automatically obtained. Loops can be placed in the programs for processing multiple blocks in the same way, e.g., using the same set of commands. However, the computer time required to perform a place and route on a typical design is very long. Should there be a problem with the execute program, or a problem with the placement or routing of the netlist, or a problem in one of the commands, then the entire execute program needs to be re-run from scratch once the problem is isolated and fixed. Therefore, this prior art approach is not very efficient in the face of design errors or program bugs which are always present. Furthermore, although this prior art approach helps to automate some of the designer""s job, it still requires that in the development or modification of the execute program, the designer needs to use and edit the low level, volumous detailed commands. As such, this development process can be tedious, error-prone and time consuming.
Another prior approach to solving the problem of dealing with these low level commands is utilize a program such as the UNIX Make, which is well known and commercially available. The program, Make, allows dependency graphs to be used indicating the input and the output of certain nodes, with each node representing a design tool task to be performed. In order to place and route the netlist, the graphs are analyzed to determined which nodes need which data and the appropriate node execution is then performed in the order dictated by the data dependencies. On subsequent re-runs of the netlist, if a node""s input has not changed since the last run, then the node is not executed and its output is similarly re-used. Although offering efficient executions, this prior approach requires that the entire physical design process be hand-coded in the low level commands required of the design tools. This approach does not offer any flexibility in dealing with similar blocks or in adding or deleting or modifying commands because any such activity must be performed by hand, with an editor, directly on the low level commands. For instance, to run the same design tool over various blocks requires that the same code be block copied for each block, e.g., using an editor. To change a variable or parameter within the design tools requires that the code portion relating to that design tools be identified and manually modified. Again, this approach is very tedious, error-prone and time consuming.
Accordingly, what is needed is a system and method for providing the flexibility offered by the xe2x80x9cexecute programsxe2x80x9d while still providing the execution efficiency offered by the dependency graphs described above. What is further needed is an efficient user interface for presenting the functionality of sophisticated integrated circuit design tools to allow their full exploitation by the user. The present invention provides these advantages and others not specifically mentioned above but described in the sections to follow.
Embodiments of the present invention are directed towards a method for implementing a user interface for performing physical design operations on an integrated circuit netlist. Embodiments of the method implement a snapping process for snapping blocks of cells to a grid of power and ground lines within the area of a chip (integrated circuit die). The snapping process provides for the snapping dimensions of the plurality of blocks to the grid such that the dimensions of the blocks align with the grid. The user interface also implements a process of using keystones and attach points to define connectivity relationships between the blocks. The connectivity relationships are defined by graphically linking the attach points of the respective blocks and updating the input file in accordance with the defined connections. Loose fly lines are displayed to graphically depict connection relationships between each of the plurality of blocks. The graphical depiction allows the alteration of the physical placement of the blocks in accordance with the revealed connectivity relationships. Master libraries and modifiable master libraries are used to match occurrences of elements within the netlist with their corresponding specifications, including those elements which do not have fixed definitions. The first master library comprises fixed elements having fixed specifications and the second modifiable library comprises modifiable elements having specifications which can change with each subsequent occurrence. The use of the two libraries allows the complete parsing of the input file (the integrated circuit netlist), thereby enabling a complete build of the integrated circuit netlist.
Specifically, a grid snapping embodiment of the present invention functions by accessing vertical and horizontal dimensions of an area of a chip and accessing a grid for power and ground lines of the chip. A view of the grid is then provided to the user on a computer display, for example, a CAD workstation display. A plurality of blocks of cells of the integrated circuit netlist are then accessed, each block representing circuit components to be realized in physical form. Dimensions of the plurality of blocks are xe2x80x9csnappedxe2x80x9d to the grid such that the dimensions of the blocks align with the grid. Thus the user can defined new dimensions and new configurations for the blocks while the interface ensures that any new dimensions are properly aligned with the grid. The dimensions of the plurality of blocks are controlled to align with the power and ground modulus of the grid such that the blocks can be linked to the power and grid lines in an interchangeable manner.
A keystone attach point embodiment of the present invention functions by accessing an input file containing identifications of a plurality of blocks of cells of said integrated circuit netlist and presenting a view of the plurality blocks to a user, the view provided by a computer display (e.g., CAD workstation display). Attach points for each block are defined and connections for the blocks are defined by graphically linking the attach points (the keystones) of the respective blocks. The linking is performed by, for example, tracing lines between the keystones using a mouse. Once linked, the input file is updated in accordance with the defined connections. The attach points for each block are graphically depicted by the view and are at predefined locations at each block (e.g., in each corner, etc.). Alternatively, the attach points can be graphically linked by the user via a textual command line interface. In either case, the view of the plurality of blocks can be updated in accordance with the newly defined connections to graphically reflect the defined connections.
A loose fly lines display embodiment of the present invention functions by accessing the input file (for the integrated circuit netlist), presenting a view of the plurality blocks to a user (e.g., CAD workstation display), and graphically depicting connection relationships between the plurality of blocks. The depiction of the connection relationships between the plurality of blocks is altered in accordance with a number of logical elements connected between the quality of blocks. The depiction visually shows connectivity relationships of the integrated circuit netlist. The number of logical elements connected between the plurality of blocks for generating the corresponding depiction is user adjustable (e.g., depending upon clutter, complexity, etc.). The type of logical elements connected between the plurality of blocks for generating the corresponding depiction is also user adjustable. The graphical depiction of connectivity relationships is used to change and/or fine-tune the physical placement configuration of at least one of the plurality of blocks to achieve a more efficient build placement.
A master library/modifiable master library embodiment of the present invention functions by accessing an input file of the integrated circuit netlist and parsing the input file to identify elements within the netlist matching corresponding elements within a first library file (master library file). At least one element within the netlist is identified, wherein the element does not have a corresponding element within the master library file. A modifiable element corresponding to the at least one element is stored within a second library file (modifiable master library file). A subsequent occurrence of the at least one element is identified within the netlist and the subsequent occurrence is matched to the modifiable element in the modifiable master library file. The parsing of the input file of the integrated circuit netlist is then completed, wherein each element comprising the input file matches corresponding elements in the first, master library or the second, modifiable master library. This allows a build of the integrated circuit netlist to be completed based on the parsed input file and specifications stored in the first library or the second library. The master library comprises fixed elements having fixed specifications, while the modifiable master library comprises modifiable elements having specifications which can change with each subsequent occurrence. The modifiable master library file contains definitions of element abstracts which can be extended in accordance with multiple occurrences of the element abstracts within the integrated circuit netlist.